1. Field of the Invention
This invention relates to a device and method for performing frequency multiplication which exhibits low phase noise. More particularly, the present invention provides for programmable frequency multiplication by using an array of Complex Frequency Shifters (CFS's) in combination with signal routing controlled by the an array of programmable switches.
2. Background of the Related Art
Frequency multipliers along with frequency dividers are among the very essential building blocks in frequency generation and synthesis devices and are extensively used in these and many other applications. Signal sources with very low phase noise are increasingly more in demand as the frequencies utilized by such devices continue to increase along with the overall performance requirements. For example, the jitter of the clock caused by phase noise limits the achievable signal-to-noise ratio “SNR” in high speed ADCs/DACs. Reducing the clock jitter improves the achievable performance and allows higher frequency operation in demanding applications. This is one example among many where a low noise frequency multiplier allows for improved operating performance.
Numerous types of frequency multipliers are known in the art (e.g., frequency doublers), and include both analog and digital based devices. Generally speaking, analog multipliers have some advantages over digital multipliers in that they can operate at higher frequencies, achieve higher multiplication ratios, have lower phase noise and lower broadband noise, and consume less power. Analog multipliers can typically be divided in two categories: direct analog multipliers and the multipliers based on multiplying phase-lock loops or other schemes employing closed loop feedback systems or injection-locking mechanisms. As explained in detail below, the present invention falls within the category of direct analog multipliers.
Direct analog multipliers can further be divided into multipliers based on parametric nonlinearities of components, for instance nonlinear conductance or capacitive reactance and those using multiplying devices, such as mixers. Discrete circuits using nonlinearities of components such as diodes or transistors have been extensively used in the prior art, but typically need to be tuned to a specific frequency range or spectral component and are narrow-band. Mixer-based multipliers are a more systematic way of performing frequency multiplication, and provide wider bandwidth capabilities and have potential for larger multiplication ratios.
A typical mixer-based frequency doubler circuit of the prior art is shown in the block diagram of FIG. 1. Referring to FIG. 1, the device includes a mixer 10 which serves as a multiplier of the input signal cos(ωt) present at input 14 with itself and thereby up-converts the frequency to a double frequency cos(2ωt) at the output 12. The amplitude of the up-converted signal is ½ of the input amplitude representing a 6 dB loss. The multiplication in mixer 10 is a double sideband conversion (DSB), meaning the multiplication also generates another sideband, a DC component in this case (term ½ at the output 12). This term is not desired because it burdens the dynamic range of the mixer 10 resulting in reduced converted signal level and consequently reduced signal to noise ratio (SNR). When compared with a single sideband conversion (SSB), the DSB conversion will exhibit a 3 dB lower SNR because only one of the two converted sidebands is used while the other one is wasted, i.e. half of the converted power is lost, resulting in a 3 dB SNR reduction. This loss of SNR adds to other circuit implementation losses and of course can not be recovered by any amount of post-mixer gain.
Another prior art multiplier circuit is illustrated in the block diagram of FIG. 2. As shown in FIG. 2, the device includes a cascade of doublers each of which contains a mixer 10. As a result, the device achieves a frequency multiplication by a factor of 2n, where n represents the number of frequency doublers (i.e., mixers). In each stage, mixer 10 is driven with signals in phase quadrature, as one of the signals coupled to the mixer is output by a quadrature splitting circuit 30. Multiplying the quadrature signals results in a product with no DC content at the output thereby improving the dynamic range. One drawback of the cascade device of FIG. 2 is that the quadrature splitting circuit 30 needs to be repeated in every stage, adding to the complexity and reducing the bandwidth (BW) of the system. The BW is reduced because the quadrature splitting circuits 30 are effectively connected in series with each other, resulting in a reduction of the aggregate BW compared with a BW of a single quadrature splitter. Since the frequency is different (i.e., doubled) at every stage, the quadrature splitter 30 at each stage is different from the other stages, and needs to be designed and tuned to a different frequency thus complicating the design and manufacturing of the device. Another drawback of this circuit is the loss of SNR due to DSB conversion, which increases the SNR degradation from stage to stage by 3 dB, as compared with SSB conversion.
While devices for performing frequency multiplication by factorial of two (2) (for instance 2, 4, 8 . . . ) have been addressed in the prior art, that is not the case for frequency multiplication by an arbitrary integer factors. Generally speaking, devices for performing frequency multiplication by an arbitrary integer factor have not been addressed in the prior art. In particular, the prior art fails to provide the frequency multiplication by an arbitrary, integer factor which is programmable. Thus, there remains a need for a programmable frequency multiplication device which provides for multiplication by arbitrary integer factors, which exhibits improved SNR and addresses the other limitations noted above.